A traditional design flow for developing ASICs, including standard cell-based ASICs, structured ASICs and other similar types of ASICs, includes a conversion from an FPGA design to an ASIC design. An FPGA-to-ASIC conversion methodology typically employs an FPGA for prototyping purposes. Once the design is proven using the FPGA prototype, the logic of the FPGA serves as a basis for subsequent development of ASIC production devices. The conversion to an ASIC generally requires modifying a functional description for an ASIC device from a functional description expressed in terms of the FPGA. A drawback to this traditional design flow is that the conversion extends time-to-market (“TTM”) and increases development costs, among other things. FIG. 1 depicts at least two design flows using conventional FPGA-to-ASIC conversion methodologies.
FIG. 1 illustrates a few conventional ASIC design flows. Design flow 101 begins with a design of programmable logic using FPGA technology 102 for prototyping purposes. After the design is proved, then the design developed for FPGAs is modified during a conversion process 104 to generate a design in a structural ASIC technology 106. Similarly, design flow 103 starts with the design of programmable logic using FPGA technology 102, followed by a conversion process 104 to develop a design in standard cell ASIC technology 108. Both design flows have a drawback of having relatively long design cycles that extends time-to-market.
In view of the foregoing, it would be desirable to minimize at least one of the drawbacks in each of the traditional ASIC design flows using programmable logic.